发送HELLO WORLD
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/09/04 19:06:31
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input reset_n,
input fpga_gclk,
output e_reset,
output e_mdc, //MDIO的时钟信号，用于读写PHY的寄存器
inout e_mdio, //MDIO的数据信号，用于读写PHY的寄存器
input e_rxc, //125Mhz ethernet gmii rx clock
input e_rxdv, //GMII 接收数据有效信号
input e_rxer, //GMII 接收数据错误信号
input [7:0] e_rxd, //GMII 接收数据
input e_txc, //25Mhz ethernet mii tx clock
output e_gtxc, //25Mhz ethernet gmii tx clock
output e_txen, //GMII 发送数据有效信号
output e_txer, //GMII 发送数据错误信号
output [7:0] e_txd //GMII 发送数据
);
assign e_gtxc = e_rxc;
assign e_reset = 1'd1;
assign e_txer = 1'd0;
reg [7:0] data_ram [13:0];
initial begin
data_ram[0] <= 8'h68; //h
data_ram[1] <= 8'h65; //e
data_ram[2] <= 8'h6c; //l
data_ram[3] <= 8'h6c; //l
data_ram[4] <= 8'h6f; //o
data_ram[5] <= 8'h20; //space
data_ram[6] <= 8'h77; //w
data_ram[7] <= 8'h6f; //o
data_ram[8] <= 8'h72; //r
data_ram[9] <= 8'h6c; //l
data_ram[10] <= 8'h64; //d
data_ram[11] <= 8'h2e; //.
data_ram[12] <= 8'h2e; //.
data_ram[13] <= 8'h2e; //.
end
reg crc_re;
reg [5:0] state;
reg [24:0] cnt;
reg [7:0] data;
reg crc_en;
wire [31:0] crc;
wire [31:0] CrcNext;
reg e_txen_r;
always @(negedge e_rxc or negedge reset_n)
begin
if(!reset_n) begin
state <= 6'd0;
cnt <= 25'd0;
crc_re <= 1'd0;
data <= 8'd0;
e_txen_r <= 1'd0;
end
else begin
case(state)
6'd0: begin
if(cnt == 25'h1ffffff) begin
cnt <= 25'd0;
state <= state + 6'd1;
end
else begin
cnt <= cnt + 25'd1;
end
data <= 8'd0;
crc_re <= 1'd1;
crc_en <= 1'd0;
e_txen_r <= 1'd0;
end
6'd1: begin
if(cnt == 25'd7) begin
cnt <= 25'd0;
state <= state + 6'd1;
data <= 8'hd5;
end
else begin
cnt <= cnt + 25'd1;
data <= 8'h55;
end
crc_re <= 1'd0;
crc_en <= 1'd1;
e_txen_r <= 1'd1;
end
6'd2: begin
if(cnt == 25'd13) begin
cnt <= 25'd0;
state <= state + 6'd1;
data <= data_ram[cnt];
end
else begin
cnt <= cnt + 25'd1;
data <= data_ram[cnt];
end
crc_re <= 1'd0;
crc_en <= 1'd1;
e_txen_r <= 1'd1;
end
6'd3: begin
crc_re <= 1'd0;
crc_en <= 1'd1;
e_txen_r <= 1'd1;
if(cnt==0) begin
data[7:0] <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]};
cnt<=cnt+1'b1;
end
else begin
if(cnt==1) begin
data[7:0]<={~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]};
cnt<=cnt+1'b1;
end
else if(cnt==2) begin
data[7:0]<={~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]};
cnt<=cnt+1'b1;
end
else if(cnt==3) begin
data[7:0]<={~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]};
cnt<=0;
state<=6'd0;
end
end
end
endcase
end
end
assign e_txd = data;
assign e_txen = e_txen_r;
crc crc_inst(
.Clk(e_rxc),
.Reset(crc_re),
.Data_in(data),
.Enable(crc_en),
.Crc(crc),
.CrcNext(CrcNext)
);
endmodule
`timescale 1ns / 1ps
module crc (Clk, Reset, Data_in, Enable, Crc,CrcNext);
parameter Tp = 1;
input Clk;
input Reset;
input [7:0] Data_in;
input Enable;
output [31:0] Crc;
reg [31:0] Crc;
output [31:0] CrcNext;
wire [7:0] Data;
assign Data={Data_in[0],Data_in[1],Data_in[2],Data_in[3],Data_in[4],Data_in[5],Data_in[6],Data_in[7]};
assign CrcNext[0] = Crc[24] ^ Crc[30] ^ Data[0] ^ Data[6];
assign CrcNext[1] = Crc[24] ^ Crc[25] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[6] ^ Data[7];
assign CrcNext[2] = Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[6] ^ Data[7];
assign CrcNext[3] = Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[7];
assign CrcNext[4] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6];
assign CrcNext[5] = Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7];
assign CrcNext[6] = Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7];
assign CrcNext[7] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[31] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[7];
assign CrcNext[8] = Crc[0] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4];
assign CrcNext[9] = Crc[1] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5];
assign CrcNext[10] = Crc[2] ^ Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5];
assign CrcNext[11] = Crc[3] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4];
assign CrcNext[12] = Crc[4] ^ Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6];
assign CrcNext[13] = Crc[5] ^ Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[6] ^ Data[7];
assign CrcNext[14] = Crc[6] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6] ^ Data[7];
assign CrcNext[15] = Crc[7] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[7];
assign CrcNext[16] = Crc[8] ^ Crc[24] ^ Crc[28] ^ Crc[29] ^ Data[0] ^ Data[4] ^ Data[5];
assign CrcNext[17] = Crc[9] ^ Crc[25] ^ Crc[29] ^ Crc[30] ^ Data[1] ^ Data[5] ^ Data[6];
assign CrcNext[18] = Crc[10] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[6] ^ Data[7];
assign CrcNext[19] = Crc[11] ^ Crc[27] ^ Crc[31] ^ Data[3] ^ Data[7];
assign CrcNext[20] = Crc[12] ^ Crc[28] ^ Data[4];
assign CrcNext[21] = Crc[13] ^ Crc[29] ^ Data[5];
assign CrcNext[22] = Crc[14] ^ Crc[24] ^ Data[0];
assign CrcNext[23] = Crc[15] ^ Crc[24] ^ Crc[25] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[6];
assign CrcNext[24] = Crc[16] ^ Crc[25] ^ Crc[26] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[7];
assign CrcNext[25] = Crc[17] ^ Crc[26] ^ Crc[27] ^ Data[2] ^ Data[3];
assign CrcNext[26] = Crc[18] ^ Crc[24] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[3] ^ Data[4] ^ Data[6];
assign CrcNext[27] = Crc[19] ^ Crc[25] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[1] ^ Data[4] ^ Data[5] ^ Data[7];
assign CrcNext[28] = Crc[20] ^ Crc[26] ^ Crc[29] ^ Crc[30] ^ Data[2] ^ Data[5] ^ Data[6];
assign CrcNext[29] = Crc[21] ^ Crc[27] ^ Crc[30] ^ Crc[31] ^ Data[3] ^ Data[6] ^ Data[7];
assign CrcNext[30] = Crc[22] ^ Crc[28] ^ Crc[31] ^ Data[4] ^ Data[7];
assign CrcNext[31] = Crc[23] ^ Crc[29] ^ Data[5];
always @ (posedge Clk, posedge Reset)
begin
if (Reset) begin
Crc <={32{1'b1}};
end
else if (Enable)
Crc <=CrcNext;
end
endmodule
转载：https://blog.csdn.net/smallerlang/article/details/100931276
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